I'm compiling hwloc using clang (bgclang++11 from ANL) to run on IO nodes af a
BGQ. It seems to have compiled ok, and when I run lstopo, I get an output like
this (below), which looks reasonable, but there are 15 sockets instead of 16.
I'm a little worried because the first time I compiled, I had problems where
apps would report an error from HWLOC on start and tell me to set
HWLOC_FORCE_BGQ=1. when I did set this env var, it would then report that
"topology became empty" and the app would segfault due to the unexpected return
from hwloc presumably.
I wiped everything and recompiled (not sure what I did differently), and now it
behaves more sensibly, but with 15 instead of 16 sockets.
Should IO be worried?
Thanks
JB
Machine (15GB)
Socket L#0 + L1d L#0 (16KB) + L1i L#0 (16KB) + Core L#0
PU L#0 (P#0)
PU L#1 (P#1)
PU L#2 (P#2)
PU L#3 (P#3)
Socket L#1 + L1d L#1 (16KB) + L1i L#1 (16KB) + Core L#1
PU L#4 (P#4)
PU L#5 (P#5)
PU L#6 (P#6)
PU L#7 (P#7)
Socket L#2 + L1d L#2 (16KB) + L1i L#2 (16KB) + Core L#2
PU L#8 (P#8)
PU L#9 (P#9)
PU L#10 (P#10)
PU L#11 (P#11)
Socket L#3 + L1d L#3 (16KB) + L1i L#3 (16KB) + Core L#3
PU L#12 (P#12)
PU L#13 (P#13)
PU L#14 (P#14)
PU L#15 (P#15)
Socket L#4 + L1d L#4 (16KB) + L1i L#4 (16KB) + Core L#4
PU L#16 (P#16)
PU L#17 (P#17)
PU L#18 (P#18)
PU L#19 (P#19)
Socket L#5 + L1d L#5 (16KB) + L1i L#5 (16KB) + Core L#5
PU L#20 (P#20)
PU L#21 (P#21)
PU L#22 (P#22)
PU L#23 (P#23)
Socket L#6 + L1d L#6 (16KB) + L1i L#6 (16KB) + Core L#6
PU L#24 (P#24)
PU L#25 (P#25)
PU L#26 (P#26)
PU L#27 (P#27)
Socket L#7 + L1d L#7 (16KB) + L1i L#7 (16KB) + Core L#7
PU L#28 (P#28)
PU L#29 (P#29)
PU L#30 (P#30)
PU L#31 (P#31)
Socket L#8 + L1d L#8 (16KB) + L1i L#8 (16KB) + Core L#8
PU L#32 (P#32)
PU L#33 (P#33)
PU L#34 (P#34)
PU L#35 (P#35)
Socket L#9 + L1d L#9 (16KB) + L1i L#9 (16KB) + Core L#9
PU L#36 (P#36)
PU L#37 (P#37)
PU L#38 (P#38)
PU L#39 (P#39)
Socket L#10 + L1d L#10 (16KB) + L1i L#10 (16KB) + Core L#10
PU L#40 (P#40)
PU L#41 (P#41)
PU L#42 (P#42)
PU L#43 (P#43)
Socket L#11 + L1d L#11 (16KB) + L1i L#11 (16KB) + Core L#11
PU L#44 (P#44)
PU L#45 (P#45)
PU L#46 (P#46)
PU L#47 (P#47)
Socket L#12 + L1d L#12 (16KB) + L1i L#12 (16KB) + Core L#12
PU L#48 (P#48)
PU L#49 (P#49)
PU L#50 (P#50)
PU L#51 (P#51)
Socket L#13 + L1d L#13 (16KB) + L1i L#13 (16KB) + Core L#13
PU L#52 (P#52)
PU L#53 (P#53)
PU L#54 (P#54)
PU L#55 (P#55)
Socket L#14 + L1d L#14 (16KB) + L1i L#14 (16KB) + Core L#14
PU L#56 (P#56)
PU L#57 (P#57)
PU L#58 (P#58)
PU L#59 (P#59)
HostBridge L#0
PCIBridge
PCI 1014:0023
--
John Biddiscombe, email:biddisco @.at.@ cscs.ch
http://www.cscs.ch/
CSCS, Swiss National Supercomputing Centre | Tel: +41 (91) 610.82.07
Via Trevano 131, 6900 Lugano, Switzerland | Fax: +41 (91) 610.82.82
