On Sun, Dec 13, 2009 at 8:49 PM, David Stephens <
[email protected]> wrote:

> This (very rough draft) article "Cross Memory Communications for Beginners"
> may help.
>
> http://www.longpelaexpertise.com.au/ezine/CrossMemoryBeginners.html
>
> David Stephens
> Lead Systems Programmer
> [email protected]
> www.longpelaexpertise.com.au <
> http://www.longpelaexpertise.com.au/images/logo.gif>
>
> Longpela Expertise - System z Mainframe Consultants
> Read new expert Mainframe articles every quarter in our LongEx Mainframe
> Quarterly <http://www.longpelaexpertise.com.au/ezine>



Corrections for the article;

(1) SRBs do NOT always run disabled. They are initially dispatched enabled
for interrupts just like any other piece of work. They only become disabled
(legally) if they obtain a spin lock such as the CPU lock. When they release
the lock they are reenabled (again, like any other piece of work)

(2) SRBs do not ALWAYS run before any TCB in the address space where they
are dispatched. SRBs that are scheduled into an enclave run at whatever
priority that enclave happens to be assigned at any given moment according
to the service goal and attainment. That priority could be higher (or LOWER)
than any other unit of work in the address space (both TCB and SRB)

(3) Using AX=1 and SSAR to another address space is not very clearly
documented by IBM because it is a violation of the MVS xmemory architecture.
You DO NEED that "complicated synchronous cross memory" code to be safe.

(4) ASC mode does not remove the need for the "other" address space to be
swapped in. You can't reliably access a swapped out address space. Most SVCs
fail with a S0F8 abend if called in AR mode.

...but not bad.

-- 
This email might be from the
artist formerly known as CC
(or not) You be the judge.

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