On 2 March 2010 16:59, McKown, John <[email protected]> wrote: > There are multiple z9 "models". Each model has its own MSU rating, which is > basically related to the number of CPs enabled and their "speed". Now, I know > that all the CPs on all z9 run same hardware speed. So, I'm wondering how > they are "knee capped"? Now, I know that the "knee capping" is done by > loading in a specific MCL. So, I'm thinking that this somehow does something > like "inserts a wait state" during instruction processing. That is, the XYZ > instruction on all z9s run in the same amount of time. But there is > "something extra" done at the end of the XYZ instruction which causes a > "wait" before the next instruction is actually executed. Am I on the right > track? Or is it done is some other strange manner?
Could be a simple as disabling (or just not using, or flushing) a certain amount of cache. It would be instructive to see how fast a program that stays in one cache line runs on a less-than-full-speed processor. But no doubt as soon as someone figures out how to exploit that, they'll put a stop to it. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
