On Thu, Oct 20, 2005 at 08:40:53PM -0300, Shmuel Metz (Seymour J.) ([EMAIL PROTECTED]) wrote: > The last couple of funky spec manuals in which I saw instruction > timings were absolutely laden with special cases. Were IBM to publish > one for the z9, it would make strong men weep.
I'm not surprised. When we got a 3090 very early in the availability (we got it on a "defense priority" statement), I coded a bunch of tiny test programs which I ran in dedicated machine time in order to try to determine the relative speeds of the 3090 vs the 3081Kx (not to be confused with the 3081KX!). At some point I just gave up because there basically weren't any rules. If I did anything like L LR LR L A ST ST it ran in n usec. Carefully adding a few more instructions in the loop, avoiding memory collisions and register-content-waits didn't really increase the execution time. If I put interspersed floating point instructions other than multiply and divide it did NOT increase the execution time. Just like on the 360/91, light amounts of floating point were free. The 360/91 FC actually listed the number of cycles required for nearly all FP instructions as zero. After reading the 3090 FC I concluded that IBM had finally resurrected the 360/91 on faster electronics, although thankfully they left out imprecise interrupts. Certain instruction streams ran not much faster on the 3090 than they did on the 3081. Other instruction streams ran many many times faster, even though if I recall the 3090 was nominally only 2-3 times the speed of the 3081 (~30 MIPS vs 14 MIPS?) The newer the hardware the more complex this gets, so how exactly would IBM publish a timing manual? /Leonard ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
