Kees, My recollection is the first WSC flash mentioning this on the 3090s was to use CPENABLE(0,0), and it has switched between 10,30 and 0,0 at least twice since then.
http://www-03.ibm.com/support/techdocs/atsmastr.nsf/032f6e163324983085256b79 007f5aec/80154cc31e2cc90d86256fa9000766e7/$FILE/CPENABLE_vz10.pdf shows some of the more recent ITR recommendations. It least it confirmed that my memory is not too dodgy. This document does not describe how the ITR is measured - is it a bunch of LPARS with equal weights and IO loads, or is there a "squashed" LPAR with a high IO rate like Joe describes. Either way it comes across as a recommendation and not a rule. I don't see why the squashed LPAR could not have CPENABLE(0,0) while the others stayed with (10,30). In the absence of CA-ASTEX or TMON I'd say %TPI would be the measure of change besides the LPAR throughput that Joe is measuring. Ron > -----Original Message----- > From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of > Vernooij, CP - SPLXM > Sent: Wednesday, February 15, 2012 6:26 AM > To: [email protected] > Subject: Re: [IBM-MAIN] Z/architecture I/O questions > > Ron, > > Do you have a source for (0,0)? > What I could find was FLASH10337, which advises (10,30) for machines up to > z10. Are there later advises, especially for z196? > > Kees. > ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
