> >it runs with only a subset of it's LCPs enabled for interrupts > I have a definite problem with the wording of this. 'Enabled for > interrupts' in my book is quite independent of the logical/physical > cp distinction. 'enabled for interrupts' is a 7 at the appropriate > point in the psw (instead of a 4 when disabled - grossly > simplified). And 'disabled for interrupts' means just that - *any* > type of interrupt, not just I/O interrupts.
> When all cps of an lpar are disabled for interrupts, then all I/O > interrupts stay waiting for the lpar to handle them, i.e. to become > enabled for interrupts again at least on one cp. This is independent > of any cpenable setting, AFAIK. The machine presents a guest I/O interrupt directly to a dispatched LP in the appropriate zone if there is a dispatched LP which is enabled in its guest PSW and interrupt subclass mask in guest CR6. If there is no such LP, the machine presents a host I/O interrupt to LPAR. Then it becomes LPAR's responsibility to present the interrupt to the guest by dispatching an appropriately enabled LP (if there is one), or setting SIE controls so that it can intercept when a guest LP becomes appropriately enabled, and then present the interrupt. Host I/O and External interrupts can be presented to a host CP even though the guest LP dispatched on that CP is disabled for guest interrupts. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
