re: http://www.garlic.com/~lynn/2012b.html#98 5 Byte Device Addresses? http://www.garlic.com/~lynn/2012b.html#100 5 Byte Device Addresses? http://www.garlic.com/~lynn/2012c.html#16 5 Byte Device Addresses? http://www.garlic.com/~lynn/2012c.html#17 5 Byte Device Addresses? http://www.garlic.com/~lynn/2012c.html#27 5 Byte Device Addresses? http://www.garlic.com/~lynn/2012c.html#28 5 Byte Device Addresses?
misc. past posts mentioning page replacement & virtual memory management http://www.garlic.com/~lynn/subtopic.html#clock and some old email http://www.garlic.com/~lynn/lhwemail.html#globallru a recent thread in comp.arch discussion started out asking about mainframe queued i/o processing (in thread on interrupt paradigm overhead) http://www.garlic.com/~lynn/2012c.html#20 M68k add to memory is not a mistake any more http://www.garlic.com/~lynn/2012c.html#23 M68k add to memory is not a mistake any more also discusses various device optimization for page i/o operations. this has survey and taxonomy of i/o systems ... including some discussion of mainframe queued i/o http://www.cs.clemson.edu/~mark/io_hist.html there is also reference to longer discussion in IBM JR&D ... which used to be available free but is journals are now behind IEEE paywall http://ieeexplore.ieee.org/Xplore/login.jsp?reload=true&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F5288520%2F5390413%2F05390415.pdf%3Farnumber%3D5390415&authDecision=-203 In '75 ... besides endicott con'ing me into doing a lot of stuff for 138/148 "ECPS" (microcode assist) ... old post with part of data used in determining "ECPS": http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist at the same time a group in POK con'ed me into doing a lot of design for 5-way SMP. The processor technology had lots of provision for microcode ... so I dropped some amount of multiprocessor dispatching complexity into the microcode (reminiscent of later intel 432 ... or current mainframe LPAR dispatch management) ... as well as a queued i/o channel interface ... superset of the later 811 (370-xa specification named for nov78 date on lot of the specifications). some past posts http://www.garlic.com/~lynn/submain.html#bounce for whatever reason, the 5-way SMP project got canceled ... but a little later reborn as 16-way SMP effort ... and some of the 3033 processor engineers were con'ed into helping in their spare-time. This saw a lot of early acceptance ... but then somebody mentioned to the head of POK, that it might be decades before MVS could effectively support 16-way SMP ... and the head of POK told the 3033 processor engineers to get their noses back to the grindstone (and stop being distracted) ... and others got invited to never visit POK again (this was all before 3033 first shipped). misc. past general posts mentioning SMP support and/or compare&swap instruction http://www.garlic.com/~lynn/subtopic.html#smp misc past posts mentioning dispatching & dynamic adaptive scheduling (also started when I was undergraduate in the 60s) http://www.garlic.com/~lynn/subtopic.html#fairshare -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
