ref:
http://www.garlic.com/~lynn/2006e.html#45 using 3390 mod-9s
http://www.garlic.com/~lynn/2006e.html#46 using 3390 mod-9s
part of the caching/electronic store discussions that on in the 70s had
to do with global LRU and global caches vis-a-vis local LRU and
partitioning.
as an undergraduate in the 60s, i had also done the global LRU stuff for
cp67
http://www.garlic.com/~lynn/subtopic.html#wsclock
about the same time, there was some work published in the literature
about working sets and local LRU strategies.
in the early 70s, there was an effort by the grenoble science center to
implement local LRU strategy for cp67 as per the academic literature.
The cambridge science center
http://www.garlic.com/~lynn/subtopic.html#545tech
was running cp67 on 360/67 with 768k of real memory (104 pageable pages
after fixed storage requirements) and my global LRU implementation.
grenoble had a 360/67 with 1mbyte of real memory (155 pageable pages
after fixed storage requirements). Cambridge with global LRU and 104
pageable pages basically supported about twice as many users (75-80) at
the same performance and response as Grenoble support with local LRU and
155 pageable pages with 30-35 users.
in the late 70s about the time the disk activity project was gathering
extensive filesystem/disk record access traces, which was then being
used for various analysis ... including a cache simulator looking at
various kinds of device, controller, channel, subsystem, and system
caching strategies. except for some specific scenarios (device-level
full-track buffer as compensation for rotational synchronization and
things like RPS-miss) ... the modeling found that for any given, fixed
amount of electronic storage (and all other things being equal), a
single "system level" cache implementation always out-performed any
cache partitioning strategy (i.e. some part of the electronic storage
partitioned into device, controller, channel, etc caches).
About the same time (late 70s) there was a big fuss being made over a
stanford phd effort that was basically covering the stuff that I had
done as an undergraduate in the 60s. This stanford phd thesis was doing
global LRU ... and some of the people that had been indoctrinated by the
local LRU papers in the academic literature were objecting to the Phd
being awarded (since global LRU conflicted with their LRU beliefs).
I was somewhat able to contribute to resolving the disagreement since
Grenoble had published ACM article on their local LRU effort (in the
early 70s) ... and I had hardcopy of some of their supporting
performance data ... as well as similar data from Cambridge system doing
local LRU (for apples to apples comparison of the two strategies running
same system, same hardware, and similar workload).
in any case there is direct correspondence between the partitioning
that occurs in local LRU cache strategies and the physical partitioning
that occurs in device and/or controller level caches.
a couple posts that referencing the lru/clock thesis and related controversy
http://www.garlic.com/~lynn/93.html#4 360/67, was Re: IBM's Project F/S ?
http://www.garlic.com/~lynn/2001c.html#10 Memory management - Page
replacement
http://www.garlic.com/~lynn/2002c.html#49 Swapper was Re: History of
Login Names
misc. other posts mentiong the lru/clock countroversy
http://www.garlic.com/~lynn/98.html#2 CP-67 (was IBM 360 DOS (was Is
Win95 without DOS...))
http://www.garlic.com/~lynn/99.html#18 Old Computers
http://www.garlic.com/~lynn/2001h.html#26 TECO Critique
http://www.garlic.com/~lynn/2002c.html#16 OS Workloads : Interactive etc
http://www.garlic.com/~lynn/2002k.html#63 OT (sort-of) - Does it take
math skills to do data processing ?
http://www.garlic.com/~lynn/2002o.html#30 Computer History Exhibition,
Grenoble France
http://www.garlic.com/~lynn/2003f.html#30 Alpha performance, why?
http://www.garlic.com/~lynn/2003f.html#55 Alpha performance, why?
http://www.garlic.com/~lynn/2003g.html#0 Alpha performance, why?
http://www.garlic.com/~lynn/2003k.html#8 z VM 4.3
http://www.garlic.com/~lynn/2003k.html#9 What is timesharing, anyway?
http://www.garlic.com/~lynn/2004.html#25 40th anniversary of IBM
System/360 on 7 Apr 2004
http://www.garlic.com/~lynn/2004b.html#47 new to mainframe asm
http://www.garlic.com/~lynn/2004g.html#13 Infiniband - practicalities
for small clusters
http://www.garlic.com/~lynn/2004o.html#7 Integer types for 128-bit
addressing
http://www.garlic.com/~lynn/2004q.html#73 Athlon cache question
http://www.garlic.com/~lynn/2005d.html#37 Thou shalt have no other gods
before the ANSI C standard
http://www.garlic.com/~lynn/2005d.html#48 Secure design
http://www.garlic.com/~lynn/2005f.html#47 Moving assembler programs
above the line
http://www.garlic.com/~lynn/2005h.html#10 Exceptions at basic block
boundaries
http://www.garlic.com/~lynn/2005n.html#23 Code density and performance?
http://www.garlic.com/~lynn/2006b.html#15 {SPAM?} Re: Expanded Storage
http://www.garlic.com/~lynn/2006b.html#35 Seeking Info on XDS Sigma 7 APL
http://www.garlic.com/~lynn/2006d.html#0 IBM 610 workstation computer
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