On 7/28/2006 9:49 AM, Wayne Driscoll wrote:
Time to talk to Bob Rogers at SHARE and see if we can get the definitive
answer.
Bob deferred to one of our senior CPU architects. More below.
From: "Edward Jaffe" <[EMAIL PROTECTED]>
Jeffrey D. Smith wrote:
Just back-up a bit in the PoPs and read the "Block-Concurrent
References" paragraph. It all depends on the size of the block.
All CPU must be using the same block-size to ensure consistent views.
A full-word block is not the same as a double-word block.
The full-word store-type access is not necessarily "widened" to a
double-word access (or quad-word on Z machines). The CPU must be using
the same alignment and block width. The PoPs does not say that
different accesses to different block sizes is concurrent.
Most importantly, it does NOT say that the block size matters when
different instructions access the same storage. The alignment and block
width does NOT matter. Doubleword concurrent is doubleword concurrent,
regardless of what other instructions are trying to modify the storage.
The full-word store is not a double-word concurrent store. Therefore
the double-word fetch is not protected from inconsistent results.
The block sizes are different. The specification only applies to the
same block access (alignment and width).
Sorry, not true, and confirmed by the CPU architect whom I asked.
Huh???! That paragraph in PoOps says:
"When a fetch-type reference is specified to appear to be concurrent
within a block, no store access to the block by another CPU is
permitted during the time that bytes contained in the block are being
fetched."
This statement is simple, not complex. It says, without caveats or
exceptional language of any kind, that the (entire) block is protected
from being updated by other CPUs until the block-concurrent fetch is
complete. It does not stipulate that another CPU's store access must be
on the same block boundary/width in order to be delayed.
Your interpretation is correct, Ed. A CPU fetching a doubleword in a
concurrent manner (as LM is defined to do when fetching from a
doubleword boundary) is protected once the fetch starts from any updates
by other CPUs.
Note, for LM, that this does depend on the doubleword alignment of the
storage operand. Consider the following example, where the operand is
initially word-aligned:
986A 4234 LM 6,10,X'234'(4)
In this case, register 6 would be loaded in a word-concurrent manner,
and registers 7-8 and 9-10 would be loaded in a doubleword-concurrent
manner.
Walt Farrell, CISSP
z/OS Security Design, IBM
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