On Fri, 28 Jul 2006 15:11:22 -0400 Walt Farrell <[EMAIL PROTECTED]> wrote:
:>Your interpretation is correct, Ed. A CPU fetching a doubleword in a
:>concurrent manner (as LM is defined to do when fetching from a
:>doubleword boundary) is protected once the fetch starts from any updates
:>by other CPUs.
:>Note, for LM, that this does depend on the doubleword alignment of the
:>storage operand. Consider the following example, where the operand is
:>initially word-aligned:
:> 986A 4234 LM 6,10,X'234'(4)
:>In this case, register 6 would be loaded in a word-concurrent manner,
:>and registers 7-8 and 9-10 would be loaded in a doubleword-concurrent
:>manner.
A follow-up, if I may.
DWORD DC 0D'0'
DC F'1,2'
Cpu0: R14 = F'1,2' (64 bits)
R15 = F'6,7'
CSG R14,R15,DWORD
Cpu1:
R14 = F'99,2'
R15 = F'99,4'
CS R14,R15,DWORD+4
If the CSG and the CS are issued at the same time, are the results defined?
Can both get a condition code of zero?
--
Binyamin Dissen <[EMAIL PROTECTED]>
http://www.dissensoftware.com
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