On Thu, 28 Sep 2006 10:38:18 -0400, Gabriel Tully <[EMAIL PROTECTED]> wrote:
> ... I think this was in reference to how some processors (MIPS) >support multiple page sizes ... Yuck! I once worked with a Burroughs 2700 series computer, and it was able to support multiple page sizes. I don't recall if they could be any arbitrary length or any power of two in length. Each program would have it's own page size based upon addressing requirements, and the number of bits in the address portion of each instruction was variable based upon the maximum relative address that it needed to reference. It seemed like kind of a slick idea, but it didn't work on a memory constrained system. We were going to implement a fairly simple check writing application for disbursements. It was apparent very early that it wasn't going to perform, but for political reasons, we implemented the entire application anyway. When it came time for the final demo of the completed application, we created a small batch containing only one check. We entered the check, proofed the batch, went through the dummy run of the check writer and aligned check forms in the line printer. To get to that point, it took an hour and a half. We couldn't print the check because the system couldn't find enough contiguous memory to bring in the next page that was needed. Memory was badly fragmented with different sized pages, many of them page fixed so they couldn't be moved. Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
