Patrick O'Keefe wrote:
I remember 3 different BPSloaders - 3-card, 7-card, and 12-card versions.
There very well could have been a 6-card loader, too.  I have no idea what
the differences were but I bet the 3-card loader didn't uspport REP cards.

IPL does a "02" read operation of 24 bytes at location zero

followed by TIC CCW to location "8" (assuming it is a CCW) and when
the I/O operation completes does a LPSW on location zero.

for three card loader, you would have

first card read by IPL button with 24 bytes containing

8 byte PSW
8 byte READ CCW for 80 bytes of 2nd card, command chained to
8 byte READ CCW for 80 bytes of 3rd card

with TIC operation to +8, the first read CCW.

you now have a 160byte program+data and the PSW is setup to start with
the first instruction just read. this small program would loop reading
(following) cards until it got to last card and then branch to the
start of the program just read.

all of this came out of BPS. In fact, the CP67 kernel process was to
collect all the CP67 kernel TXT files and slap BPS loader on the
front. The BPS loader resolves all the ESD symbols and when finished
branchs to the address/symbol in the LDT card ... which pointed to the
"SAVECP" entry point. SAVECP would take the freshly loaded
core/storage image and write it to disk.

The CCWs were compatible between cards and tape ... so you could have
actual physical cards ... and/or have placed card image on tape and
performed the IPL operation on tape drive (instead of card reader).

in cp67 and vm370, the 3card loader was used to slap on the front of
single module "stand alone" utilities (like DDR, physical tape<->disk
copy routine).

3card loader could handle card deck containing single assemble, TXT

BPS loader could handle card deck with multiple TXT decks ... needing
to resolve ESDs adcons between TXT decks

a couple old posts mentioning 3card loader: sysprog shortage - what questions would 
you ask? "Bootstrap"

CP67 didn't originally ship with source for the BPS loader (although
it shipped with source for everything else). One of the modifications
I made at the university involved changes to support "paging" portions
of the (fixed) cp67 kernel ... the process I used created a quite a
few new ESD entry symbols. Basic BPS loader provided with CP67 only
supported 256 ESD symbols ... which I managed to exceed. It was real
pain trying to deal with the number of ESD limitation until i found a
copy of the BPS loader source that i could fix/modify.

The simplest way then to create a "new" BPS loader was to assemble the
source and slap a 3card loader on the front of the BPS TXT file.

Even easier was to include 3 assembler "PUNCH" statements in the source of the stand-alone utility (including the BPS assembler source) that punched hex image for the 3card loader (in front of the TXT deck being generated).

this has discussion of 3card loader in conjunction with DDRXA

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