On Thu, 31 May 2007 17:42:36 +0300, Binyamin Dissen wrote: >On Thu, 31 May 2007 06:06:18 -0700 Edward Jaffe wrote: > >:>http://shareew.prod.web.sba.com/client_files/callpapers/attach/SHARE_in_Baltimore/S8192DB073718.pdf > >Interesting reading. But I do understand the concept of address stalls. > >A SAM** should not require extra cycles and should not cause problems in the >predictive execution.
Still, it's hard for me to imagine that a few extra cycles for a SAM* instruction would have a measurable performance impact unless there were millions of them issued in a short time. Even then, the effects of cache misses would likely be far greater. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
