On Mon, 31 Dec 2007 07:31:53 -0500, Shmuel Metz (Seymour J.) wrote: >In <[EMAIL PROTECTED]>, on 12/31/2007 > at 12:38 AM, Ed Gould <[EMAIL PROTECTED]> said: > >>>The book actually had instruction timing specifics for each >>>instruction. > >If you look at the Functional Specifications for several models, you will >see that the formulae get progressively more complicated for the faster >and newer models. I believe that that's the reason IBM stopped publishing >them.
When processors srarted to include High-Speed Buffers, now commonly called cache, any published timings became very difficult to determine. When memory references were simple real memory references, the time required for each was easily determined. With the HSB, a memory reference took some number of clock cycles it the data were in the HSB and longer id they had to be fetched from main store. Sometimes still longer if a line in the buffer had to be written back to main store first. Of course, virtual address translation addes yet another layer of complexity to the time required to access storage. Worst case is a memory reference to get the segment table entry, another to get the page table entry and a third to access the storage required. Then if the data referenced crosses a segment boundary, another memory reference to get the next segment table entry and the page table entry. Translation Lookaside Buffers are used to keep these references to a minimum. These effects are one of the biggest reasons why instruction timings tend to vary. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
