Thanks to all who responded. Matt >>> Patrick Lyon <[EMAIL PROTECTED]> 1/4/2008 1:16 PM >>> On Fri, 4 Jan 2008 11:04:30 -0500, Matt Dazzo <[EMAIL PROTECTED]> wrote:
>Is there anyway to create a latch problem on a test PDSE to test the restartable STC? > >Thanks Matt > Way back when in 2.7 days (OS/390) latch issues would happen quite often. I unfortunately got good at freeing them. It seemed to me that they happened a lot when the processor was pegged, i.e. when the owner of the PDSE that had the latch was not getting enough CPU time to finish whatever they were doing and other address spaces were requesting the PDSE. I wouldn't know how to go about causing such a situation. Perhaps 2 batch jobs, one that had a PDSE with a disp=old and one disp=shr on the PDSE and they both used some type of time delay, like the BPXBATCH sleep option or something. It just seems to me that when we got to z/OS the latch issues seemed to go away. I believe a lot of effort has gone into internal code to help latches fix themselves, and hats off to the OS developers for that. All I know is when there are latch issues, don't go off issuing a FORCE on the offending latch holder. That would leave the latch in SMS but the address space was gone. I would have to code up a call to RTM to knock out the offending TCB. "There is a grave ugliness in our country". :) At least that was in 2.7 days. Good luck. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
