On Sun, 3 Feb 2008 08:21:34 -0500, Shmuel Metz (Seymour J.) wrote: >Long ago in a galaxy far away, IBM introduced the concept of resumeable >instructions; an interrupt could occur in the middle of the instruction >execution and the instruction would continue properly after a normal >dispatch. It appears that CLCL and MVCL were not only the first such long >instructions but also the last. Subsequent long instructions have required >testing the condition code to see whether the instruction had been >interrupted in media res. Superficially that seems like extraneous >overhead. Can anybody cast any light on why IBM went that way? > What can I think of?
o Special treatment in microcode for saving the PSW on interrupt? Only the resumable instructions need to store the PSW before execution. o Special branch prediction for instruction pipelining. This might be simplified by the manifest BC after repeatable instructions. But I'd expect any interrupt to void the pipeline regardless. And I believe it was stated on this list that BCT(R) is always predicted taken; all other conditional branches not taken. This might seem an adverse convention for a BC after a repeatable instruction. But aren't both cans of worms already opened by CLCL and MVCS, irreversibly unless those two instructions are relegated to millicode and deprecated in favor of nonresumable instructions (CLCG? MVCG?). Are millicode sequences interruptable? o Page faults? How are page faults handled for resumable instructions? Is a fault generated for any page in the range of either operand, with the OS attempting to stage both, or does a fault possibly for each resumption. -- gil ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
