Shmuel Metz (Seymour J.) wrote:
In <[EMAIL PROTECTED]>, on 02/03/2008
at 10:01 PM, Binyamin Dissen <[EMAIL PROTECTED]> said:
I think it is because these storage to storage operations can take so
long to execute, so long that the CPU would assume a problem and go into
a check-stop.
How does that differ from the newer long instructions? In both cases an
interrupt can be taken in the middle, and in both cases the interrupt
processing must update the general registers. The only difference between
the resumeable long instructions and the newer ones is whether the
interrupt processing backs up the PSW IC or sets a condition code.
The "new" instructions operate exactly like other non-interruptible
instructions. They process a model dependent information unit size
(often just 256 bytes) with each non-interruptible execution of the
instruction. They are much "cheaper" to implement because software
handles any needed iteration.
--
Edward E Jaffe
Phoenix Software International, Inc
5200 W Century Blvd, Suite 800
Los Angeles, CA 90045
310-338-0400 x318
[EMAIL PROTECTED]
http://www.phoenixsoftware.com/
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