The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] (Tom Marchant) writes:
> I don't know what you mean when you say the cache line was split across
> domains. I forget whether a line was 32 bytes, but it always cantained the
> data from a line of storage. The cache was split into an instruction cache
> and
> a data cache, though. There was significant logic needed to deal with that.
801/risc ("harvard") architecture allowed for independent instruction
and data caches ... but didn't provide for hardware cache
consistency. this met that self-modifying instructions were out ... and
for "store-into" data caches (which didn't automatically flush every
change to storage) ... there were special "flush" cache instruction for
use by loaders (i.e. program loaders have peculiar characteristic that
they can be treating instructions as data ... which then have to get out
to storage ... before the changes can possibly show up in the
instruction cache).
amdahl's machine at the time was somewhat viewed as remarkable being
able to provide i-cache and d-cache consistency.
a few old posting discussing 5880
http://www.garlic.com/~lynn/2006b.html#38 blast from the past ... macrocode
http://www.garlic.com/~lynn/2006e.html#31 MCTS
http://www.garlic.com/~lynn/2006j.html#35 Code density and performance?
http://www.garlic.com/~lynn/2006u.html#27 Why so little parallelism?
http://www.garlic.com/~lynn/2006u.html#34 Assembler question
http://www.garlic.com/~lynn/2006v.html#20 Ranking of non-IBM mainframe builders?
including some old email from the period (which includes reference
to 5880 announcement with separate instruction and data cache):
http://www.garlic.com/~lynn/2006b.html#email810318
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