Yea, I think I'm just about to get to that "oh" moment.
Had a really unique one last week. Had never seen this before.
My SRB executing on pr 02 did the following in that order:
PC entered POST to post an ecb a task was waiting on
then immediately on return, updated a count field in a data area,
decrementing it by one.
SPLAT...0C4.
Trace table showed the PC for the POST, then the SSRV with a timestamp.
Nothing more on pr 02 till the 0C4.
On Pr 00, my waiting task gets dispatched by the ecb post. It then
posts 2 other tasks to do some work. Both of them get dispatched.
the 2nd task to get dispatched deleted the data area the SRB wanted to
update, to decrement a count.
finally, my SRB has the entries for the program check.
Evidently, lpar processing steals processors and MVS has no knowledge of
it.
When I wrote the code, I made the mistake of figuring that an SRB would
be dispatched before a task. That looks to be the case if the SRB is
waiting to run. But, the only thing I can figure is
that pr/sm stole it, so the SRB didn't get interrupted, and placed on
any kind of a waiting to dispatch queue.
Always learning something new...
--Dave
On 9/17/2012 3:25 PM, Blaicher, Christopher Y. wrote:
Dave day said, "The runchain IPCS command showed me the error, I just have to figure
out how I created the error in the 1st place."
Isn't it always the case. How the heck did I do THAT? Then, once you see it, you have
an embarrassed "oh".
Chris Blaicher
Senior Software Engineer, Software Services
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8260 | M: 512-627-3803
E: [email protected]
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