On Mon, 17 Sep 2012 15:42:20 -0500 Dave Day <[email protected]> wrote:
:>When I wrote the code, I made the mistake of figuring that an SRB would :>be dispatched before a task. That looks to be the case if the SRB is :>waiting to run. But, the only thing I can figure is :>that pr/sm stole it, so the SRB didn't get interrupted, and placed on :>any kind of a waiting to dispatch queue. Either way you need to be prepared that the TCB is dispatched on one CPU while the SRB cpu is finishing up the POST. You cannot guarantee that two instructions will actually be issued in sequence (as seen by the programs on other CPUs) unless you use some kind of semaphore or lock. -- Binyamin Dissen <[email protected]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
