As you have observed, there is no support for "PSW". I'm curious what SLIP trap you're setting that would let you even know to look at "+4". You'd have to know that the instruction itself was a branch and that it was one of "your" branches. If you really could tell that it was one of your branches, and if you have a reg that you can afford to use consistently perhaps use BRAS instead of J and then you could indirect off of the value in the reg.
If this is a PER-SB (or IF) trap, and you know the address is below 2G, field LCCAPERA contains the address of the instruction that took the PER interrupt. LCCAPPSW contains the resulting PSW (so LCCAPPSW+4 contains the address, but may have bit 0 on) The LCCA is pointed to by PSA location x'210'. LCCXLCCAPERA and LCCXPPSW16_2 contain the 8-byte address and 16-byte PSW analogs. With use of an expression using indirection starting at x'210' and the EQ or EQA comparand you might be able to do something. Peter Relson z/OS Core Technology Design ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
