I see it as the opposite. I would not have expected R0 to address data.
But in the case of MVCL R0 is explicitly specified, (unlike other instructions where 0 is the absence of a base/index register) so that may be why they allowed it to address data. Perhaps the hardware cannot use AR0 in that way. On Mon, 17 Mar 2025 18:32:21 +0000 Richard Zierdt <[email protected]> wrote: :>The following is documented in PoPs, but what the hey. :>Primary (ASC) Mode: MVCL R0,Rx is fine :>AR (ASC) Mode: MVCL R0,Rx is *not* fine AR0 is not honored :>The PoPs manual on MVCL: :>"In the access-register mode, the contents of access :>register R1 and access register R2 are compared. If :>the R1 or R2 field is zero, 32 zeros are used rather :>than the contents of access register 0. " :>There is probably a reason why AR0 is not supported as MVCL operands; it's just that it's inconsistent with the corresponding behavior in Primary ACS mode. :>Richard Zierdt :>Confidentiality Warning/Avertissement de confidentialité: :>This message is intended only for the named recipients. This message may contain information that is privileged or confidential. If you are not the named recipient, its employee or its agent, please notify us immediately and permanently destroy this message and any copies you may have. Ce message est destiné uniquement aux destinataires dûment nommés. Il peut contenir de l'information privilégiée ou confidentielle. Si vous n'êtes pas le destinataire dûment nommé, son employé ou son mandataire, veuillez nous aviser sans tarder et supprimer ce message ainsi que toute copie qui peut en avoir été faite. -- Binyamin Dissen <[email protected]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
