> Is there an instruction that waits for all CPU's to be enabled at least once?
No. Bind Break does a SIGP EMS (via the RISGNL macro) to every processor, and RISGNL spins until the target processor accepts and processes the EMS external interrupt, and it has to be enabled to accept the interrupt. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY > > CPU Offline processing turns off the CSD alive bit, and zeros the > > PCCAVT and LCCAVT entries for the CPU that is going offline. Then > > a Bind Break is done, and this does not complete until every other > > CPU has enabled at least once. After that, the LCCA, PCCA, and PSA > > can be freed. So if you disable, and then fetch a non-zero address > > for a PCCA from the PCCAVT or LCCA from the LCCAVT, the PCCA, LCCA, > > and associated PSA will not be freed as long as you remain disabled. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
