Early in my career I developed a habit when writing ASM code. In 'working storage', code DS/DC fields in this order unless some other structural sequence is required: double words first, then full words, half words, and finally character (C or X) fields of whatever length. Most macros generate their own alignment instructions. Always heed alignment warnings from the assembler.
. . J.O.Skip Robinson Southern California Edison Company Electric Dragon Team Paddler SHARE MVS Program Co-Manager 626-302-7535 Office 323-715-0595 Mobile [email protected] From: Lloyd <[email protected]> To: [email protected], Date: 06/01/2014 06:12 PM Subject: Re: Is there a significant performance penalty for non-aligned operands? Sent by: IBM Mainframe Discussion List <[email protected]> On 6/1/2014 7:51 PM, Peter Relson wrote: > I believe the answer is "no", all other things being equal. > > But if one of those "other things" is that the non-aligned operand spans > cache lines whereas an aligned one would not, then the answer could be a > huge "yes". > > Things such as doubleword (or quadword) consistency could not be relied > upon, depending on the degree of non-alignment. > > Peter Relson > z/OS Core Technology Design > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to [email protected] with the message: INFO IBM-MAIN > There are times, though, when things have to be aligned for specific instructions whether hardware instructions or supervisor calls (not necessarily SVC) that things HAVE to be on a doubleword or quadword boundary. What I usually do then is defne a variable larger by the appropriate number of bytes and verify by shifting the address that I am aligned. Lloyd ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
