[email protected] (John McKown) writes: > ​Yes. I remember some decades back reading that CISC was going to die due > to RISC performing better with optimizing compilers​. That both did and > didn't come true. The hardware exposed ISA is dominated by CISC on the high > end (RISC ISA chips that I know of are ARM, Sparc, and MIPS) but the > hardware internally is more like RISC. Conceptually, a bit like what IBM > did with the TIMI for the i systems. Except that TIMI, from what I've read, > is actually compiled into native code on the first execution and is store > in a "hidden" portion of the executable on disk. Said compiled code is > "foot printed" and recompiled if the TIMI object is change or, sometimes, > when maintenance is applied to the i system software. I found the concept > fascinating.
re: http://www.garlic.com/~lynn/2015.html#44 z13 "new"(?) characteristics from RedBook low&mid range 360/370s were vertical microcode with standard cisc engines. in the late 70s an effort was started to move the large number of internal microprocessors to 801/risc (mostly 801/risc "Iliad" chips) ... including all of the 370 native engines (4361/4381 followon to 4331/4341), the as/400 (aka i-system,) and numerous controllers. For various reasons all of these efforts faultered (and you found various 801/risc engineers leaving and going to other vendors, spawning their risc projects) and reverting to business-as-usual cisc. A decade after as/400 ships with cisc, it (finally) migrated to (risc/801) power/pc. some past posts mention 801/risc, iliad, romp, rios, fort knox, power, power/pc, etc http://www.garlic.com/~lynn/subtopic.html#801 one of the earliest such efforts was the AMD 29K (and IBM may have sued AMD because former 801/risc engineer worked on it). Some (former) IBMers showed up working on HP "snake" risc ... and later Itanium. 801/risc as the native engine for microcoded 370 ... including some work on just-in-time (JIT) "compiling" ... sequences of 370 code segments dynamically translated to native risc (instead of repeated straight interpretation). Equivalent JIT was later done for some of the i86-based 370 simulators ... and analogous JIT is being done for JAVA. other trivia, AIM/Somerset (applie, ibm, motorola) for single chip 801/risc (aka power/pc) somewhat combined 801/risc rios with Motorola's 88k risc (internal IBM 801/risc had long history of not supporting cache consistency making multiprocessor implementations difficult, Motorolo's 88k did have cache consistency support). The pentium-pro translate from i86 to risc could be considered similar to (long history of) 360/370 microcoded implementations ... but at the hardware layer and pipelined. The 360/370 microcode implementations typically avg. 10 native instructions for every 360/370 instruction and since they were serialized, it needed a 10mip processor to get 1mip 360/370. The pentium-pro pipelined just needed 1mip native since it was doing several things, concurrently, in parallel with the pipeline. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
