On Sat, Jul 18, 2015 at 11:43 PM, Shmuel Metz (Seymour J.) < [email protected]> wrote:
> In <[email protected]>, on > 07/17/2015 > at 07:03 PM, Paul Schuster <[email protected]> said: > > >I have to do a LG R1,64bitfield and then a LTGR R1,R1 and then > >the JZ. > > LTG R1,64bitfield > JZ NULL > > >I'm sure this was not overlooked by the engineers, > > Well, I'd like an ICMG with an 8-bit mask for more general use. -- > ​Hum, just contemplating this. And wondering why IBM didn't do it. There are a lot of other instructions in the ISA which seem, to me, to have lesser utility. So I'm just posting some rambling thoughts. There is the ICM and ICMH which, combined, could be use to emulate this. I am looking in the -10 POPS manual on the various instruction formats. I am not a hardware engineer. But I guess that such formats are standardized in order to group them into "classes". Each of which has some sort of hardware support. There appear, to me, to be four classes of instructions which are what I think of as pertaining to a single register as a direct operand (as opposed to indirect such as use in a base or index). RX (two subclasses), RXY (two subclasses), RSY (two subclasses). The current "Insert Character" instructions are in the RX (subclass a), RXY (subclass a), RS (subclass b), and RSY (subclass b). All of these "classes" have all of their bits utilized. So there's no room in them for another 4 bits of mask. The only format in the -10 POPS which currently has 8 bits of masking is the VRR class, subclasses -b, -d, and -e. But that doesn't seem like a good class in which to put a "IC" type instruction. Just doesn't "fit" aesthetically. Actually, there is not _any_ currently defined "class", as described on page 5-4 of the -10 POPS, into which such an "IC" instruction could fit. Now, the RXE format has 4 unused bits in it. So perhaps the engineers could make that into two subclasses A "-a" subclass which only uses 4 bits as at present, and a "-b" subclass which uses all 8 bit. That gets us an IC with base+12 bit displacement. Now we need to find where to put base+20 bit displacement and an "immediate". For the immediate, they could use a new RIE variant (it already has 7) which has a 8 bit mask, similar to the "-a" variant which has a 4 bit mask. As best as I can see, this would require a new RSL subclass which has an 8 bit mask. I have _no_ idea how complicated it is to implement a new instruction format. But that is the first thing which would be required to implement an IC type instruction which does 8 bits. Seems a bit much for a single instruction. As an aside, if the CC is unimportant, then simply doing an ICM followed by an ICMH should suffice. If the CC is important, that is a bit more difficult. And today is Sunday and I'm not in the mood to try to figure out how to do it in a macro. But I'm sure that it's possible by using another register and SPM/IPM to maintain the condition code properly. > Shmuel (Seymour J.) Metz, SysProg and JOAT > ISO position; see <http://patriot.net/~shmuel/resume/brief.html> > We don't care. We don't have to care, we're Congress. > (S877: The Shut up and Eat Your spam act of 2003) > > -- Schrodinger's backup: The condition of any backup is unknown until a restore is attempted. Yoda of Borg, we are. Futile, resistance is, yes. Assimilated, you will be. He's about as useful as a wax frying pan. 10 to the 12th power microphones = 1 Megaphone Maranatha! <>< John McKown ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
