On 19 July 2015 at 11:27, John McKown <[email protected]> wrote: > Hum, just contemplating this. And wondering why IBM didn't do it. There > are a lot of other instructions in the ISA which seem, to me, to have > lesser utility. So I'm just posting some rambling thoughts. > > I am looking in the -10 POPS manual on the various instruction formats. I am > not a hardware engineer. But I guess that such formats are standardized in > order to group them into "classes". Each of which has some sort of hardware > support. There appear, to me, to be four classes of instructions which are > what I think of as pertaining to a single register as a direct operand (as > opposed to indirect such as use in a base or index). RX (two subclasses), > RXY (two subclasses), RSY (two subclasses). [...] > Actually, there is not _any_ currently defined "class", as described on > page 5-4 of the -10 POPS, into which such an "IC" instruction could fit. > Now, the RXE format has 4 unused bits in it. So perhaps the engineers could > make that into two subclasses A "-a" subclass which only uses 4 bits as at > present, and a "-b" subclass which uses all 8 bit. That gets us an IC with > base+12 bit displacement.
> Now we need to find where to put base+20 bit > displacement and an "immediate". For the immediate, they could use a new > RIE variant (it already has 7) which has a 8 bit mask, similar to the "-a" > variant which has a 4 bit mask. As best as I can see, this would require a > new RSL subclass which has an 8 bit mask. I don't think for the likely uses for an ICMG that there is much call for a Y version. In most code I've seen, except where it is being used like LT, ICM is typically used with a zero or small displacement from a moving "base" register that is really a very local base for a data item. A more important constraint, or at least consideration, is that the mask field should be modifiable by an EXecute instruction, as it is with ICM[x]. This constrains the mask to being in bits 8-15 of the instruction, which could therefore be a single-byte opcode or a two-byte one where the second byte is not in bits 8-15. I don't think there are any instructions that, as you put it "pertain[...] to a single register as a direct operand (as opposed to indirect such as use in a base or index)" that have that target register not specified in bits 8-15. Another approach would be an instruction of RR[x] format, where the storage operand address is in a register, and the mask is in either a specified register or a hardcoded one (R0, perhaps). This might even allow for a mask of more than 8 bits (64, presumably), leading to a sort of ICMD scheme where the mask applies to more than one register. With the mask in a register, the ability to specify the mask via EXecute becomes unimportant. Well, small fantasies for a Monday morning. Presumably the compiler writers who seem to generate hardware design these days have found no use for such schemes. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
