On Sat, Mar 19, 2016 at 9:50 PM, Tom Marchant < [email protected]> wrote:
> <snip> > > > I'm skeptical of all that but assuming all that, where are they going to > get the I/O > bandwidth needed? > I wonder that myself. But then, there are now SSD devices which run directly on the PCIe bus at PCIe bus speeds. I could envision a purpose built system (likely way too expensive) which has an Intel Xeon class CPU for regular instructions, a GPU array using CUDA for numeric intensive work, and "channels" made up of ARM processors, each controlling only a few SSD (SATA 3 or PCIe attached) drives sharing memory with the main system memory for I/O. > > -- > Tom Marchant > -- A fail-safe circuit will destroy others. -- Klipstein Maranatha! <>< John McKown ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
