For the SLLG, SRLG, SRAG and others, if you load the B register with the number of bits to shift and set the D value to zero, you can shift a variable number of bits without using an EXECUTE instruction.
And there are SRL, SRDL, SRAG and SRLG that rotate right. Chris Blaicher Technical Architect Mainframe Development Syncsort Incorporated 50 Tice Boulevard, Woodcliff Lake, NJ 07677 P: 201-930-8234 | M: 512-627-3803 E: [email protected] www.syncsort.com -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Charles Mills Sent: Friday, June 24, 2016 3:59 PM To: [email protected] Subject: Re: Simple assembler question > there are no versions of these instruction that rotate right... Blatant liberal* slant? Interesting. I was just looking at these instructions, which I have never used. The rotate count is an immediate operand, and not an immediate operand modifiable by Execute. Is there no way to rotate by an amount in a register, other than by modifying an instruction in storage, or with a loop? For those like me who have trouble remembering the mapping between facilities and models, the high word facility comes along with the z196. *Liberal in the American political sense, for our European and Asian members. Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Tony Harminc Sent: Friday, June 24, 2016 12:15 PM To: [email protected] Subject: Re: Simple assembler question On 23 June 2016 at 17:51, Phil Smith III <[email protected]> wrote: > > With all of the 273 new formats of LOAD, I assume this is hiding in there > somewhere: > I have a value in grande register 3. I need the high-order bits in > 32-bit R0 and the low-order bits in 32-bit R15. The RxSB... instructions are marvels in several ways, not least for having in some cases five operands, and in some cases 7-character names. And because there are some extended assembler mnemonics that bear no resemblance to the name or description of the base instruction. RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits]. There is an extended mnemonic LLHFR (presumably Load Low from High Fullword Register) that generates RISBLGZ R1,R2,0,31,32 but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on the "Zero remaining bits" flag. These are actually great instructions for all sorts of things, and are recommended for performance reasons in Kevin Shum's IBM z Systems Processor Optimization Primer. If there's a catch, it's that they require the High Word Facility. I must admit I spent an embarassing number of minutes wondering why there are no versions of these instruction that rotate right... ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN ________________________________ ATTENTION: ----- The information contained in this message (including any files transmitted with this message) may contain proprietary, trade secret or other confidential and/or legally privileged information. Any pricing information contained in this message or in any files transmitted with this message is always confidential and cannot be shared with any third parties without prior written approval from Syncsort. This message is intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the intended recipient, you are on notice that any use, disclosure, copying or distribution of this message, in any form, is strictly prohibited. If you have received this message in error, please immediately notify the sender and/or Syncsort and destroy all copies of this message in your possession, custody or control. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
