On Thu, Dec 29, 2016 at 1:01 PM, Paul Gilmartin <
[email protected]> wrote:
> On Thu, 29 Dec 2016 10:18:43 -0800, Ed Jaffe wrote:
> >
> >Windows -- like all operating systems -- has an RB chain equivalent.
> >
> >The big difference is the S/360 hardware did not have a hardware stack
> >so the operating system implemented everything via software structures.
> >Thus, the RB chain was born. Intel and other later architectures had
> >hardware stacks from the beginning, so much of that context is
> >maintained in hardware structures.
> >
> >If something like the ESA/390 linkage stack existed back in the S/360
> >days, there might never have been RBs.
> >
> I understand that threads (of some variety) are implemented as TCBs.
>
> I'd expect a "linkage stack" to operate LIFO ("stack", after all). Isn't
> the RB chain more flexible? I thought IRBs take priority over other
> RBs.
>
RB are chained from the TCB. The TCB points to the running RB. That RB
either points to the previous RB in the chain to back to the TCB. If it
points to the TCB, when the code does a "top level return" (R14 from when
the original program was invoked) or "exit" (SVC 3) task termination occurs.
IRBs are "special" in that they are used for "asynchronous exits". What
occurs is that "something happens" and an IRB is placed at the head of the
chain (pointed at by the TCB).
For example, a STIMER REAL request expires. I.e. a "timer pops", which is
set to drive some user code in the application. The STIMER has created an
IRB. The timer pop has already saved the status of the running program in
the RB, so the "pop code" uses the SCHEDIRB macro to schedule the IRB. This
simply places the IRB onto the RB chain. When the TCB is next dispatched,
the values in the IRB (regs & PSW) are loaded and the asynchronous exit
runs. When the code exits (SVC 3 or returns via R14), the IRB is unchained
and the suspended RB simply restarts right where it was interrupted.
I use STIMER REAL when I want to wait for something but also need a timeout
value. I get the "something" running. It will POST and ECB when it
finishes. I then do the STIMER REAL. I then wait on 1 or 2 possible ECBs
(WAIT 1,ECBLIST=). If the STIMER pops, my exit code gets control, under an
IRB, and it does a POST of the 2nd ECB. My code then exits. This satisfies
the WAIT so the RB is dispatched in the next instruction after the WAIT.
Which is where I test to see which ECB was posted.
Note that I sometimes say that "the RB is dispatched", but what I really
mean is "The TCB is dispatched which causes z/OS to reload the regs & PSW
from the values in the current RB, which pointed to by the TCBRBP field of
the TCB."
<snip>
> -- gil
>
>
--
Heisenberg may have been here.
http://xkcd.com/1770/
Maranatha! <><
John McKown
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