Re: VFM Vs Flash Express: Much simpler management of VFM resource (HMC task) No hardware repair and verify (no cables, no adapters) Better performance since no “I/O” to attached adapter takes place. Doesn't use I/O slots. RAS: Memory protected by RAIM and ECC (internal / main memory)
Re: 10 core/5.2 GHZ/14 nm Customer benefits from the overall technology i.e. latest chip design, more function on the same size chip (CPACF, Compression, cache, reduced latency between the PU/SC chips and between CPC drawers etc. Overall more performance when compared to prior generation PU chips. Cache Improvements: New power efficient logical directory design 33% larger L1 I$ (128K) 2x larger L2 D$ (4MB) 2x larger L3 Cache with symbol ECC New Translation/TLB2 design 4 concurrent translations Reduced latency Lookup integrated into L2 access pipe 2x CRSTE growth 1.5X PTE growth New 64 entry 2gig TLB2 Pipeline Optimizations Improved instruction delivery Faster branch wakeup Reduced execution latency Optimized 2nd generation SMT2 Better Branch Prediction 33% Larger BTB1 & BTB2 New Perceptron Predictor New Simple Call Return Stack ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
