[email protected] (Parwez Hamid) writes: > z14 Key H/W high-lights: > > Up to 170 Customer PUs @ 5.2 GHz each on a 14 nm 10 core chip > Up to 32 TB Memory > Uni = 1832 'mips', 170-way = 146462 'mips'
z900, 16 processors, 2.5BIPS (156MIPS/proc), Dec2000 z990, 32 processors, 9BIPS, (281MIPS/proc), 2003 z9, 54 processors, 18BIPS (333MIPS/proc), July2005 z10, 64 processors, 30BIPS (469MIPS/proc), Feb2008 z196, 80 processors, 50BIPS (625MIPS/proc), Jul2010 EC12, 101 processors, 75BIPS (743MIPS/proc), Aug2012 z13, 141 processors, 100BIPS (710MIPS/proc), Jan2015 ... z14, 170 processor, 146.5 BIPS, (862MIPS/proc - half uni), Aug2017 z196 documentation claims that half the per processor performance improvement (compared to z10), is the introduction of out-of-order execution (compared to being used for decades in other processors) ... i.e. half of 156MIPS increase from 469MIPS to 625MIPS. out-of-order helps to mask huge latency in memory access ... potentially allowing execution of other instructions while waiting on cache miss. added to out-of-order execution are branch prediction and speculative execution ... 360/195 had just out-of-order execution ... but conditional branches drained the pipeline ... most codes ran at only half the 195 rated mip-rate (5mips rather than 10mips). Current latency to memory, when measured in number of processor cycles ... is comparable to 60s disk access latency, when measured in number of 60s processor cycles. almost 18yrs, the number of processors increase by factor of ten times, while per processor performance increase by 5.5 times ... overall increase 58.6 times. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
