On Fri, 26 Jul 2019 at 08:52, Mike Schwab <[email protected]> wrote:
> Well, the hardware does move a 256 byte area aligned on a 256 bytes > boundary very efficiently. And would allow you to load the register > with an address without storing the last byte. So a storage pool with > allocation of multiples of 256 bytes would greatly helped. > I thought of that... But then for generality maybe the instruction should be something like Load and Zero Rightmost Sufficient-to-address-a-cache-line Bits. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
