1. Speed within the highest level cache are publish, along with the slowdown for lower levels of cache. Paging in speeds are not covered. 2. Varies between processors. 3. If you can avoid base and index registers, you can gain quite a bit of speed by avoiding address arithmetic. And I think the have a greater than 4k of addressability range.
On Mon, Aug 12, 2019, 19:48 Brian Chapman <[email protected]> wrote: > Hi everyone, > > I did some searching, but I didn't find anything that really discussed this > on the topic that I'm interested. Is there anything published that compares > the cycle times of the most used instructions? > > For example; moving an address between areas of storage. I would assume > that executing a LOAD and STORE would be much quicker than executing a MVC. > > Or executing a LOAD ADDRESS to increment a register instead of ADD HALF > WORD. > > Or does this really matter as much as ordering the instructions so they are > optimized for the pipeline? > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to [email protected] with the message: INFO IBM-MAIN > ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
