Worse than you imagine, a time-out. Regards, Richard Schuh
-----Original Message----- From: The IBM z/VM Operating System [mailto:[EMAIL PROTECTED] On Behalf Of Alan Altmark Sent: Friday, July 20, 2007 1:01 PM To: [email protected] Subject: Re: IUCV Interruptions On Friday, 07/20/2007 at 03:43 EDT, "Schuh, Richard" <[EMAIL PROTECTED]> wrote: > Next question/problem. The folks working on z/TPF say that they have > ported the code to perform IUCV from TPF 4.1 to z/TPF and have made the > changes for mask bits and address requirements and do not get any IUCV > interrupts on the TPF machine. The other side is a CMS machine that acts > as a driver. It has not been altered in any way. I have asked the > obvious question about the IUCV DECLARE BUFFER and got a reply that was > an indignant "yes". And they have also unmasked by turning CR0, bit 62 > on and unmasked the PSW. Do you have any idea why they would not receive > the IUCV interrupts? What did the CMS machine get on its IUCV CONNECT? If they hadn't done a Declare Buffer, you would have gotten CC=1 and IPCODE = 0x0c. If no errors, then a #CP TRACE EXT 4000 RUN and #CP TRACE IUCV RUN on the TPF machine is appropriate. If you got CC=0, do you get any other IUCV interrupts on the CMS side? (Use the same traces.) Alan Altmark z/VM Development IBM Endicott
