On Thu, 29 Apr 2010 14:26:38 -0700 Eric Anholt <[email protected]> wrote:
> On Wed, 21 Apr 2010 11:39:24 -0700, Jesse Barnes > <[email protected]> wrote: > > This allows us to do less cache flushing on 965+ chipsets. > > I don't think this commit is correct. The ring processing will > continue past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before > the pipeline is flushed. > > I suspect that squashing this with later commits may make for a > correct change, though. Sorry I didn't split these very well; squash them if needed or kick them back to me and I'll repost. Thanks, Jesse _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
