On Tue, Mar 15, 2011 at 07:59:48AM +0000, Chris Wilson wrote: > I think I should update the comments to reflect what the spec says about > LOAD_REGISTER_IMM (even though I trust Daniel to have accurately > determined their impact on gen2/3)... The spec implies that the variable > length nature of the command is to handle 32/64 bit writes as opposed to > batch multiple writes into a single (ideally atomic) command.
I've derived my knowledge about load_reg_imm from staring at the hw context layout in the public docs (where this command seems to be used). I don't recall how extensively I've tested it (iirc only had a i855gm back then) put it got the job done. On re-reading that stuff I've noticed that 2 MI_NOOP follow immediately, maybe that's part of the secret sauce? The load_reg_imm docs (at least the public variants) seem to completely drop the variable length thingy. At least the table looks fixed-length and the length = Total Length - 2 blurb is standard for all multi-word commands. -Daniel -- Daniel Vetter Mail: [email protected] Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
