With the snb blt workaround gone, gen5 pipe_control is the only user of
ring->private. It's already tiny, but make it even smaller to prepare for
embedding. The added indirection will be killed in the next patch.

Signed-off-by: Daniel Vetter <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    8 +++-----
 1 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index afb2a34..c73410f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -213,7 +213,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
 struct pipe_control {
        struct drm_i915_gem_object *obj;
        volatile u32 *cpu_page;
-       u32 gtt_offset;
 };
 
 static int
@@ -243,7 +242,6 @@ init_pipe_control(struct intel_ring_buffer *ring)
        if (ret)
                goto err_unref;
 
-       pc->gtt_offset = obj->gtt_offset;
        pc->cpu_page =  kmap(obj->pages[0]);
        if (pc->cpu_page == NULL)
                goto err_unpin;
@@ -400,7 +398,7 @@ pc_render_add_request(struct intel_ring_buffer *ring,
        struct drm_device *dev = ring->dev;
        u32 seqno = i915_gem_get_seqno(dev);
        struct pipe_control *pc = ring->private;
-       u32 scratch_addr = pc->gtt_offset + 128;
+       u32 scratch_addr = pc->obj->gtt_offset + 128;
        int ret;
 
        /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
@@ -417,7 +415,7 @@ pc_render_add_request(struct intel_ring_buffer *ring,
 
        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
                        PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
-       intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+       intel_ring_emit(ring, pc->obj->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
        intel_ring_emit(ring, seqno);
        intel_ring_emit(ring, 0);
        PIPE_CONTROL_FLUSH(ring, scratch_addr);
@@ -434,7 +432,7 @@ pc_render_add_request(struct intel_ring_buffer *ring,
        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
                        PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
                        PIPE_CONTROL_NOTIFY);
-       intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+       intel_ring_emit(ring, pc->obj->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
        intel_ring_emit(ring, seqno);
        intel_ring_emit(ring, 0);
        intel_ring_advance(ring);
-- 
1.7.4.2

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