This gets display and 2D blit acceleration up and running. No Render
acceleration is provided yet.
---
src/i965_render.c | 4 ++++
src/intel_batchbuffer.c | 4 +++-
src/intel_driver.h | 9 +++++++++
src/intel_module.c | 16 ++++++++++++++++
4 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/src/i965_render.c b/src/i965_render.c
index bfcd3f2..b76107d 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -182,6 +182,10 @@ i965_check_composite(int op,
int width, int height)
{
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ if (IS_GEN7(intel))
+ return FALSE;
/* Check for unsupported compositing operations. */
if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 289ed2b..7b3de26 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -218,7 +218,9 @@ void intel_batch_submit(ScrnInfoPtr scrn)
ret = drm_intel_bo_mrb_exec(intel->batch_bo,
intel->batch_used*4,
NULL, 0, 0xffffffff,
- IS_GEN6(intel) ? intel->current_batch:
I915_EXEC_DEFAULT);
+ (HAS_BLT(intel) ?
+ intel->current_batch:
+ I915_EXEC_DEFAULT));
}
if (ret != 0) {
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 2e72177..180281e 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -184,6 +184,13 @@
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */
#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
+
+#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
+#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
+#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
+#define PCI_CHIP_IVYBRIDGE_D_GT1_SERVER 0x015a
+#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
+
#endif
#define I85X_CAPID 0x44
@@ -209,6 +216,7 @@
#define IS_GEN4(intel) IS_GENx(intel, 4)
#define IS_GEN5(intel) IS_GENx(intel, 5)
#define IS_GEN6(intel) IS_GENx(intel, 6)
+#define IS_GEN7(intel) IS_GENx(intel, 7)
/* Some chips have specific errata (or limits) that we need to workaround. */
#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
@@ -222,6 +230,7 @@
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
+#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60)
extern SymTabRec *intel_chipsets;
diff --git a/src/intel_module.c b/src/intel_module.c
index 6cf5951..13f1635 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -73,6 +73,10 @@ static const struct intel_device_info intel_sandybridge_info
= {
.gen = 60,
};
+static const struct intel_device_info intel_ivybridge_info = {
+ .gen = 70,
+};
+
static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -116,6 +120,11 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_SANDYBRIDGE_M_GT2, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge" },
+ {PCI_CHIP_IVYBRIDGE_M_GT1, "Ivybridge Mobile GT1" },
+ {PCI_CHIP_IVYBRIDGE_M_GT2, "Ivybridge Mobile GT2" },
+ {PCI_CHIP_IVYBRIDGE_D_GT1, "Ivybridge Desktop GT1" },
+ {PCI_CHIP_IVYBRIDGE_D_GT1_SERVER, "Ivybridge Desktop Server GT1" },
+ {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop GT2" },
{-1, NULL}
};
SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
@@ -173,6 +182,13 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,
&intel_sandybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
+
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1_SERVER, &intel_ivybridge_info
),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
+
{ 0, 0, 0 },
};
--
1.7.4.4
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