On Wed, 07 Dec 2011 10:35:45 -0800 Eric Anholt <e...@anholt.net> wrote:
> On Sat, 22 Oct 2011 19:41:24 -0700, Ben Widawsky <b...@bwidawsk.net> wrote:
> > The docs say this is required for Gen7, and since the bit was added for
> > Gen6, we are also setting it there pit pf paranoia. Particularly as
> > Chris points out, if PIPE_CONTROL counts as a 3d state packet.
> >
> > This was found through doc inspection by Ken and applies to Gen6+;
> >
> > Cc: Keith Packard <kei...@keithp.com>
> > Reported-by: Kenneth Graunke <kenn...@whitecape.org>
> > Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> > Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
> > Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
>
> Reviewed-by: Eric Anholt <e...@anholt.net>
>
> however, it doesn't appear to help Ivybridge IRQ troubles.
You could try something like the below to force the use of PIPE_NOTIFY
instead. Only lightly tested on IVB when we had lots of other bugs, so
I'm not sure if it works at all.
--
Jesse Barnes, Intel Open Source Technology Center
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 60e4b9e..ce045a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -62,7 +62,7 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
MODULE_PARM_DESC(semaphores,
"Use semaphores for inter-ring sync (default: false)");
-unsigned int i915_enable_rc6 __read_mostly = 1;
+unsigned int i915_enable_rc6 __read_mostly = 0;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
MODULE_PARM_DESC(i915_enable_rc6,
"Enable power-saving render C-state 6 (default: true)");
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 02f96fd..4ab2e90 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -568,7 +568,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
atomic_inc(&dev_priv->irq_received);
if (IS_GEN6(dev))
- bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
+ bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT | GT_PIPE_NOTIFY;
/* disable master interrupt before clearing iir */
de_ier = I915_READ(DEIER);
@@ -602,7 +602,7 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
notify_ring(dev, &dev_priv->ring[RCS]);
if (gt_iir & bsd_usr_interrupt)
notify_ring(dev, &dev_priv->ring[VCS]);
- if (gt_iir & GT_BLT_USER_INTERRUPT)
+ if (gt_iir & (GT_BLT_USER_INTERRUPT | GT_PIPE_NOTIFY))
notify_ring(dev, &dev_priv->ring[BCS]);
if (de_iir & DE_GSE)
@@ -1810,7 +1810,8 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
render_irqs =
GT_USER_INTERRUPT |
GT_GEN6_BSD_USER_INTERRUPT |
- GT_BLT_USER_INTERRUPT;
+ GT_BLT_USER_INTERRUPT |
+ GT_PIPE_NOTIFY;
else
render_irqs =
GT_USER_INTERRUPT |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47b9b27..0a67334 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -292,8 +292,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
I915_WRITE(MI_MODE, mode);
}
- if (INTEL_INFO(dev)->gen >= 6) {
- } else if (IS_GEN5(dev)) {
+ if (INTEL_INFO(dev)->gen >= 5) {
ret = init_pipe_control(ring);
if (ret)
return ret;
@@ -411,10 +410,13 @@ pc_render_add_request(struct intel_ring_buffer *ring,
* incoherence by flushing the 6 PIPE_NOTIFY buffers out to
* memory before requesting an interrupt.
*/
- ret = intel_ring_begin(ring, 32);
+ ret = intel_ring_begin(ring, 38);
if (ret)
return ret;
+ update_semaphore(ring, 0, seqno);
+ update_semaphore(ring, 1, seqno);
+
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
@@ -1289,12 +1291,10 @@ int intel_init_render_ring_buffer(struct drm_device
*dev)
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
*ring = render_ring;
- if (INTEL_INFO(dev)->gen >= 6) {
- ring->add_request = gen6_add_request;
+ if (INTEL_INFO(dev)->gen >= 5) {
+ ring->add_request = pc_render_add_request;
ring->irq_get = gen6_render_ring_get_irq;
ring->irq_put = gen6_render_ring_put_irq;
- } else if (IS_GEN5(dev)) {
- ring->add_request = pc_render_add_request;
ring->get_seqno = pc_render_get_seqno;
}
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