On Tue, 03 Jan 2012 19:40:36 -0800, Ben Widawsky <[email protected]> wrote: > On 12/29/2011 05:52 PM, Eric Anholt wrote: > > These registers are automatically incremented by the hardware during > > transform feedback to track where the next streamed vertex output > > should go. Unlike the previous generation, which had a packet for > > setting the corresponding registers to a defined value, gen7 only has > > MI_LOAD_REGISTER_IMM to do so. That's a secure packet (since it loads > > an arbitrary register), so we need to do it from the kernel, and it > > needs to be settable atomically with the batchbuffer execution so that > > two clients doing transform feedback don't stomp on each others' > > state. > > > > Instead of building a more complicated interface involcing setting the > > registers to a specific value, just set them to 0 when asked and > > userland can tweak its pointers accordingly. > > > > Signed-off-by: Eric Anholt<[email protected]>
> > +/** Resets the SO write offset registers for transform feedback on gen7. */
> > +#define I915_EXEC_GEN7_SOL_RESET (1<<8)
> > +
> > struct drm_i915_gem_pin {
> > /** Handle of the buffer to be pinned. */
> > __u32 handle;
>
> Is this something we want to carry long term wrt ABI. I really want to
> get context/ppgtt stuff out the door relatively soon (context should be
> ready to test really soon actually).
>
> I'm totally unfamiliar with this register, but is this what you want the
> interface to be permanently?
Ultimately, we want this ABI plus contexts. Until then, we can live
with this ABI alone.
pgpilHxVAU9RG.pgp
Description: PGP signature
_______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
