On Sat, Jan 28, 2012 at 20:48, Daniel Vetter <daniel.vet...@ffwll.ch> wrote:
> The drm core _really_ likes to frob around with the crtc timings and > put halfed vertical timings (in fields) in there. Which confuses the > overlay code, resulting in it's refusal to display anything at the > lower half of an interlaced pipe. > > Tested-by: Christopher Egert <cme3...@gmail.com> > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch> > This makes sense, and we have a test-case where it actually solves issues. So Reviewed-by: Eugeni Dodonov <eugeni.dodo...@intel.com> -- Eugeni Dodonov <http://eugeni.dodonov.net/>
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