This attempts to enable all the available power wells during the initialization.
Signed-off-by: Eugeni Dodonov <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b3dc15..2c5b953 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9142,6 +9142,34 @@ static void i915_disable_vga(struct drm_device *dev) POSTING_READ(vga_reg); } +/* Starting with Haswell, we have different power wells for + * different parts of the GPU. This attempts to enable them all. + */ +static void intel_init_power_wells(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long power_wells[] = { + HSW_PWR_WELL_CTL1, + HSW_PWR_WELL_CTL2, + HSW_PWR_WELL_CTL4 + }; + int i; + + mutex_lock(&dev->struct_mutex); + + for (i = 0; i < ARRAY_SIZE(power_wells); i++) { + int well = I915_READ(power_wells[i]); + + if ((well & HSW_PWR_WELL_STATE) == 0) { + I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); + if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) + DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); + } + } + + mutex_unlock(&dev->struct_mutex); +} + void intel_modeset_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -9159,6 +9187,9 @@ void intel_modeset_init(struct drm_device *dev) intel_init_quirks(dev); + if (IS_HASWELL(dev)) + intel_init_power_wells(dev); + intel_init_display(dev); if (IS_GEN2(dev)) { -- 1.7.9.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
