On Wed, 21 Mar 2012 12:48:26 -0700 Jesse Barnes <[email protected]> wrote:
> ValleyView and similar hardware (like CedarView) put some display > related registers like the PLL controls and dividers on a DPIO bus. Add > simple indirect register access routines to get to those registers. > > Signed-off-by: Jesse Barnes <[email protected]> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++ > drivers/gpu/drm/i915/i915_reg.h | 55 ++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_display.c | 76 > ++++++++++++++++++++++++++++++++++ > 3 files changed, 135 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 83ace70..0294330 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -354,6 +354,10 @@ typedef struct drm_i915_private { > > /* protects the irq masks */ > spinlock_t irq_lock; > + > + /* DPIO indirect register protection */ > + spinlock_t dpio_lock; > + > /** Cached value of IMR to avoid reads in updating the bitfield */ > u32 pipestat[2]; > u32 irq_mask; I am not convinced we need the dpio_lock. Can't we just use struct_mutex or the mode.config mutex? I'm not terribly opposed, more curious than anything else. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index af5cd25..ad6b5e0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -301,6 +301,61 @@ > #define DEBUG_RESET_RENDER (1<<8) > #define DEBUG_RESET_DISPLAY (1<<9) > > +/* > + * DPIO - a special bus for various display related registers to hide behind: > + * 0x800c: m1, m2, n, p1, p2, k dividers > + * 0x8014: REF and SFR select > + * 0x8014: N divider, VCO select > + * 0x801c/3c: core clock bits > + * 0x8048/68: low pass filter coefficients > + * 0x8100: fast clock controls > + */ > +#define DPIO_PKT 0x2100 > +#define DPIO_RID (0<<24) > +#define DPIO_OP_WRITE (1<<16) > +#define DPIO_OP_READ (0<<16) > +#define DPIO_PORTID (0x12<<8) > +#define DPIO_BYTE (0xf<<4) > +#define DPIO_BUSY (1<<0) /* status only */ > +#define DPIO_DATA 0x2104 > +#define DPIO_REG 0x2108 > +#define DPIO_CTL 0x2110 > +#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ > +#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ > +#define DPIO_SFR_BYPASS (1<<1) > +#define DPIO_RESET (1<<0) > + > +#define _DPIO_DIV_A 0x800c > +#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ > +#define DPIO_K_SHIFT (24) /* 4 bits */ > +#define DPIO_P1_SHIFT (21) /* 3 bits */ > +#define DPIO_P2_SHIFT (16) /* 5 bits */ > +#define DPIO_N_SHIFT (12) /* 4 bits */ > +#define DPIO_ENABLE_CALIBRATION (1<<11) > +#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ > +#define DPIO_M2DIV_MASK 0xff > +#define _DPIO_DIV_B 0x802c > +#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) > + > +#define _DPIO_REFSFR_A 0x8014 > +#define DPIO_REFSEL_OVERRIDE 27 > +#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ > +#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ > +#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ > +#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ > +#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ > +#define _DPIO_REFSFR_B 0x8034 > +#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) > + > +#define _DPIO_CORE_CLK_A 0x801c > +#define _DPIO_CORE_CLK_B 0x803c > +#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) > + > +#define _DPIO_LFP_COEFF_A 0x8048 > +#define _DPIO_LFP_COEFF_B 0x8068 > +#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, > _DPIO_LFP_COEFF_B) > + > +#define DPIO_FASTCLK_DISABLE 0x8100 > > /* > * Fence registers > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index de1ba19..b8daeef 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -360,6 +360,79 @@ static const intel_limit_t > intel_limits_ironlake_display_port = { > .find_pll = intel_find_pll_ironlake_dp, > }; > > +#define wait_for_atomic_us(COND, US) ({ \ > + int i, ret__ = -ETIMEDOUT; \ > + for (i = 0; i < (US); i++) { \ > + if ((COND)) { \ > + ret__ = 0; \ > + break; \ > + } \ > + udelay(1); \ > + } \ > + ret__; \ > +}) It'd be much friendlier if you put this with the other wait_for code in intel_drv.h > + > +#if 0 > +static u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) > +{ > + unsigned long flags; > + u32 val = 0; > + > + spin_lock_irqsave(&dev_priv->dpio_lock, flags); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { > + DRM_ERROR("DPIO idle wait timed out\n"); > + goto out_unlock; > + } > + > + I915_WRITE(DPIO_REG, reg); > + I915_WRITE(DPIO_PKT, reg); > + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | > + DPIO_BYTE); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { > + DRM_ERROR("DPIO read wait timed out\n"); > + goto out_unlock; > + } > + val = I915_READ(DPIO_DATA); > + > +out_unlock: > + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); > + return val; > +} > +#endif I've not read the spec at all, but it looks suspicious that you write reg to DPIO_PKT, followed by a value presumably overwriting reg. Maybe a comment to clarify why two back to back writes to the same register (without a posting read)? > + > +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, > + u32 val) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&dev_priv->dpio_lock, flags); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { > + DRM_ERROR("DPIO idle wait timed out\n"); > + goto out_unlock; > + } > + > + I915_WRITE(DPIO_DATA, val); > + I915_WRITE(DPIO_REG, reg); > + I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | > + DPIO_BYTE); > + if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) > + DRM_ERROR("DPIO write wait timed out\n"); > + > +out_unlock: > + spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); > +} > + > +static void vlv_init_dpio(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + /* Reset the DPIO config */ > + I915_WRITE(DPIO_CTL, 0); > + POSTING_READ(DPIO_CTL); > + I915_WRITE(DPIO_CTL, 1); > + POSTING_READ(DPIO_CTL); > +} > + > static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, > int refclk) > { > @@ -9187,6 +9260,9 @@ void intel_modeset_cleanup(struct drm_device *dev) > if (IS_IRONLAKE_M(dev)) > ironlake_disable_rc6(dev); > > + if (IS_VALLEYVIEW(dev)) > + vlv_init_dpio(dev); > + > mutex_unlock(&dev->struct_mutex); > > /* Disable the irq before mode object teardown, for the irq might _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
