On Wed, Oct 26, 2016 at 03:41:36PM +0200, Maarten Lankhorst wrote: > There's no need to keep a duplicate skl_pipe_wm around any more, > everything can be discovered from crtc_state, which we pass around > correctly now even in case of plane disable. > > The copy in intel_crtc->wm.skl.active is equal to > crtc_state->wm.skl.optimal after the atomic commit completes. > It's useful for two-step watermark programming, but not required for > gen9+ which does it in a single step. We can pull the old allocation > from old_crtc_state. > > Signed-off-by: Maarten Lankhorst <[email protected]> > Cc: Matt Roper <[email protected]> > Reviewed-by: Paulo Zanoni <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_drv.h | 1 - > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++---------- > 3 files changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 48eb0635ec0f..592a6ec354a7 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -13478,7 +13478,7 @@ static void verify_wm_state(struct drm_crtc *crtc, > return; > > skl_pipe_wm_get_hw_state(crtc, &hw_wm); > - sw_wm = &intel_crtc->wm.active.skl; > + sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; > > skl_ddb_get_hw_state(dev_priv, &hw_ddb); > sw_ddb = &dev_priv->wm.skl_hw.ddb; > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 73be640fad36..77a0a73e37b0 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -723,7 +723,6 @@ struct intel_crtc { > /* watermarks currently being used */ > union { > struct intel_pipe_wm ilk; > - struct skl_pipe_wm skl; > } active; > > /* allow CxSR on this pipe */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 5ff35833b258..fe4bc97ed56a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3930,11 +3930,11 @@ bool skl_ddb_allocation_overlaps(struct > drm_atomic_state *state, > } > > static int skl_update_pipe_wm(struct drm_crtc_state *cstate, > - struct skl_ddb_allocation *ddb, /* out */ > + const struct skl_pipe_wm *old_pipe_wm, > struct skl_pipe_wm *pipe_wm, /* out */ > + struct skl_ddb_allocation *ddb, /* out */ > bool *changed /* out */) > { > - struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc); > struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); > int ret; > > @@ -3942,7 +3942,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state > *cstate, > if (ret) > return ret; > > - if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm))) > + if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm))) > *changed = false; > else > *changed = true; > @@ -4177,10 +4177,12 @@ skl_compute_wm(struct drm_atomic_state *state) > for_each_crtc_in_state(state, crtc, cstate, i) { > struct intel_crtc_state *intel_cstate = > to_intel_crtc_state(cstate); > + const struct skl_pipe_wm *old_pipe_wm = > + &to_intel_crtc_state(crtc->state)->wm.skl.optimal; > > pipe_wm = &intel_cstate->wm.skl.optimal; > - ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm, > - &changed); > + ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, > + &results->ddb, &changed); > if (ret) > return ret; > > @@ -4224,8 +4226,6 @@ static void skl_update_wm(struct drm_crtc *crtc) > if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) > return; > > - intel_crtc->wm.active.skl = *pipe_wm; > - > mutex_lock(&dev_priv->wm.wm_mutex); > > /* > @@ -4395,10 +4395,8 @@ void skl_wm_get_hw_state(struct drm_device *dev) > > skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); > > - if (intel_crtc->active) { > + if (intel_crtc->active) > hw->dirty_pipes |= drm_crtc_mask(crtc); > - intel_crtc->wm.active.skl = cstate->wm.skl.optimal; > - } > } > > if (dev_priv->active_crtcs) { > -- > 2.7.4 > -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
