On Thu, Apr 26, 2012 at 03:21:09PM -0300, Eugeni Dodonov wrote:
> On Haswell, only one pipe can work in FDI mode, so this patch prevents
> messing with wrong registers when FDI is being used by non-first pipe.
>
> Signed-off-by: Eugeni Dodonov <[email protected]>
I think we need to restrict the vga encoder to pipe 0 with possible_crtcs,
otherwise userspace won't figure out why vga just won't work. Can you
please add this to this patch? Also, please add a small note to the commit
message that fdi should work on any pipe, we're just making our lifes
easier for now ...
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b2d3dc1..6509402 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -978,9 +978,14 @@ static void assert_fdi_rx(struct drm_i915_private
> *dev_priv,
> u32 val;
> bool cur_state;
>
> - reg = FDI_RX_CTL(pipe);
> - val = I915_READ(reg);
> - cur_state = !!(val & FDI_RX_ENABLE);
> + if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe
> > 0\n");
> + return;
> + } else {
> + reg = FDI_RX_CTL(pipe);
> + val = I915_READ(reg);
> + cur_state = !!(val & FDI_RX_ENABLE);
> + }
> WARN(cur_state != state,
> "FDI RX state assertion failure (expected %s, current %s)\n",
> state_string(state), state_string(cur_state));
> @@ -1013,6 +1018,10 @@ static void assert_fdi_rx_pll_enabled(struct
> drm_i915_private *dev_priv,
> int reg;
> u32 val;
>
> + if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + DRM_ERROR("Attempting to enable FDI on Haswell with pipe >
> 0\n");
> + return;
> + }
> reg = FDI_RX_CTL(pipe);
> val = I915_READ(reg);
> WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should
> be active but is disabled\n");
> @@ -1484,6 +1493,10 @@ static void intel_enable_transcoder(struct
> drm_i915_private *dev_priv,
> assert_fdi_tx_enabled(dev_priv, pipe);
> assert_fdi_rx_enabled(dev_priv, pipe);
>
> + if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + DRM_ERROR("Attempting to enable transcoder on Haswell with pipe
> > 0\n");
> + return;
> + }
> reg = TRANSCONF(pipe);
> val = I915_READ(reg);
> pipeconf_val = I915_READ(PIPECONF(pipe));
> --
> 1.7.10
>
> _______________________________________________
> Intel-gfx mailing list
> [email protected]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: [email protected]
Mobile: +41 (0)79 365 57 48
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
