Resent with proper --in-reply-to . Please ignore.
On Fri, 2016-11-11 at 15:31 +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is mostly backwards compatible with broxton, so change most
> of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> platforms will be implemented in follow-up patches.
>
> v2: Don't reuse broxton's path in intel_update_max_cdclk().
> Don't set plane count as in broxton.
>
> v3: Rebase
>
> v4: Include the check intel_bios_is_port_hpd_inverted().
> Commit message.
>
> v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.
> com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
> drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++----------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 28 ++++++++++++++--------------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
> drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 17 files changed, 70 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b681d42..5d349d6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1128,7 +1128,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
> int max_freq;
>
> rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> } else {
> @@ -1224,7 +1224,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
> seq_printf(m, "Down threshold: %d%%\n",
> dev_priv->rps.down_threshold);
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -1237,7 +1237,7 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -5185,7 +5185,7 @@ static void gen9_sseu_device_status(struct
> drm_i915_private *dev_priv,
> u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
>
> /* BXT has a single slice and at most 3 subslices. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> s_max = 1;
> ss_max = 3;
> }
> @@ -5219,7 +5219,7 @@ static void gen9_sseu_device_status(struct
> drm_i915_private *dev_priv,
> for (ss = 0; ss < ss_max; ss++) {
> unsigned int eu_cnt;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a5fafa3..36483a2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -377,7 +377,7 @@ static void kunmap_page_dma(struct drm_i915_private
> *dev_priv, void *vaddr)
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> @@ -2946,7 +2946,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64
> size)
> * resort to an uncached mapping. The WC issue is easily caught by
> the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(to_i915(ggtt->base.dev)))
> + if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3078,7 +3078,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>
> ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
>
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> @@ -3319,7 +3319,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device
> *dev)
> ggtt->base.closed = false;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b..081b3b7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> found = true;
> }
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> if (tmp_mask) {
> bxt_hpd_irq_handler(dev_priv,
> tmp_mask,
> @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> }
> }
>
> - if (IS_BROXTON(dev_priv) && (iir &
> BXT_DE_PORT_GMBUS)) {
> + if (IS_GEN9_LP(dev_priv) && (iir &
> BXT_DE_PORT_GMBUS)) {
> gmbus_irq_handler(dev_priv);
> found = true;
> }
> @@ -3379,7 +3379,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
> } else {
> de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> @@ -3390,7 +3390,7 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> GEN8_PIPE_FIFO_UNDERRUN;
>
> de_port_enables = de_port_masked;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> else if (IS_BROADWELL(dev_priv))
> de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> @@ -4215,7 +4215,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3361d7f..1be2a7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2920,7 +2920,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_US(us) : \
> INTERVAL_1_33_US(us)) : \
> INTERVAL_1_28_US(us))
> @@ -2929,7 +2929,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_TO_US(interval) : \
> INTERVAL_1_33_TO_US(interval)) : \
> INTERVAL_1_28_TO_US(interval))
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 5ab646e..bd705f9 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1765,7 +1765,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private
> *dev_priv,
> {
> int i;
>
> - if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> + if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> return false;
>
> for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0ad4e16..a129ffa 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
>
> hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return hdmi_level;
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> hsw_ddi_clock_get(encoder, pipe_config);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> }
>
> @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> else
> @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port, encoder-
> >type);
>
> return DDI_BUF_TRANS_SELECT(level);
> @@ -2246,7 +2246,7 @@ void intel_ddi_init(struct drm_device *dev, enum port
> port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev_priv) && port == PORT_A) {
> + if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES
> for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 01dbf1b..723ff9d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private
> *dev_priv,
> INTELPllInvalid("m1 out of range\n");
>
> if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> - !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> + !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_BROXTON(dev_priv)) {
> + !IS_GEN9_LP(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -10675,7 +10675,7 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -10721,7 +10721,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
>
> active = hsw_get_transcoder_state(crtc, pipe_config,
> &power_domain_mask);
>
> - if (IS_BROXTON(dev_priv) &&
> + if (IS_GEN9_LP(dev_priv) &&
> bxt_get_dsi_transcoder_state(crtc, pipe_config,
> &power_domain_mask)) {
> WARN_ON(active);
> active = true;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 117a714..675e103 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int
> **source_rates)
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> int size;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> *source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct
> drm_i915_private *dev_priv,
>
> memset(regs, 0, sizeof(*regs));
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> pps_idx = bxt_power_sequencer_idx(intel_dp);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> pps_idx = vlv_power_sequencer_pipe(intel_dp);
> @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct
> drm_i915_private *dev_priv,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_BROXTON(dev_priv))
> + if (!IS_GEN9_LP(dev_priv))
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_INFO(dev)->gen >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct
> drm_i915_private *dev_priv,
> return ibx_digital_port_connected(dev_priv, port);
> else if (HAS_PCH_SPLIT(dev_priv))
> return cpt_digital_port_connected(dev_priv, port);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(dev_priv, port);
> else if (IS_GM45(dev_priv))
> return gm45_digital_port_connected(dev_priv, port);
> @@ -4932,7 +4932,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> *dev_priv,
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_BROXTON(dev_priv)) {
> + if (!IS_GEN9_LP(dev_priv)) {
> I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
> @@ -4950,7 +4950,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> *dev_priv,
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT;
> if (tmp > 0)
> @@ -5081,7 +5081,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5107,7 +5107,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5115,7 +5115,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x,
> PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev_priv) ?
> + IS_GEN9_LP(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)
> :
> I915_READ(regs.pp_div));
> }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 21853a1..8205c1c 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1861,7 +1861,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 4e0d025..4e19fbc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder
> *encoder,
> /* DSI uses short packets for sync events, so clear mode flags for
> DSI */
> adjusted_mode->flags = 0;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /* Dual link goes to DSI transcoder A. */
> if (intel_dsi->ports == BIT(PORT_C))
> pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder
> *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder
> *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder
> *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -663,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV
> */
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -755,12 +755,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> *encoder,
> * configuration, otherwise accessing DSI registers will hang the
> * machine. See BSpec North Display Engine registers/MIPI[BXT].
> */
> - if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> + if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> goto out_put_power;
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> + i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -785,7 +785,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> *encoder,
> if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> continue;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 tmp = I915_READ(MIPI_CTRL(port));
> tmp &= BXT_PIPE_SELECT_MASK;
> tmp >>= BXT_PIPE_SELECT_SHIFT;
> @@ -973,7 +973,7 @@ static void intel_dsi_get_config(struct intel_encoder
> *encoder,
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1065,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1152,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1241,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> + if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1451,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> @@ -1492,7 +1492,7 @@ void intel_dsi_init(struct drm_device *dev)
> * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI
> DSI
> * port C. BXT isn't limited like this.
> */
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
> BIT(PIPE_C);
> else if (port == PORT_A)
> intel_encoder->crtc_mask = BIT(PIPE_A);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..cf8c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
> int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(to_i915(encoder->base.dev)))
> + if (IS_GEN9_LP(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder
> *encoder,
>
> bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return bxt_dsi_pll_is_enabled(dev_priv);
>
> MISSING_CASE(INTEL_DEVID(dev_priv));
> @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder,
> enum port port)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index fb88e32..034ec1a2 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1246,7 +1246,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> @@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> *dev_priv,
>
> switch (port) {
> case PORT_B:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_1_BXT;
> else
> ddc_pin = GMBUS_PIN_DPB;
> break;
> case PORT_C:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_2_BXT;
> else
> ddc_pin = GMBUS_PIN_DPC;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 83f260b..1606e31 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> *dev_priv,
> unsigned int pin)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return &gmbus_pins_bxt[pin];
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return &gmbus_pins_skl[pin];
> @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> *dev_priv,
> {
> unsigned int size;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_skl);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> b/drivers/gpu/drm/i915/intel_mocs.c
> index 80bb924..eed0707 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private
> *dev_priv,
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->table = broxton_mocs_table;
> result = true;
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index be4b4d5..bf2899d 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
> *panel)
> intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> return;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> panel->backlight.setup = bxt_setup_backlight;
> panel->backlight.enable = bxt_enable_backlight;
> panel->backlight.disable = bxt_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cc9e0c0..dcf5cd4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5228,7 +5228,7 @@ int sanitize_rc6_option(struct drm_i915_private
> *dev_priv, int enable_rc6)
> if (!enable_rc6)
> return 0;
>
> - if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> DRM_INFO("RC6 disabled by BIOS\n");
> return 0;
> }
> @@ -5262,7 +5262,7 @@ static void gen6_init_rps_frequencies(struct
> drm_i915_private *dev_priv)
> /* All of these values are in units of 50MHz */
>
> /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
> dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
> @@ -7642,7 +7642,7 @@ void intel_init_clock_gating_hooks(struct
> drm_i915_private *dev_priv)
> dev_priv->display.init_clock_gating =
> skylake_init_clock_gating;
> else if (IS_KABYLAKE(dev_priv))
> dev_priv->display.init_clock_gating =
> kabylake_init_clock_gating;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> else if (IS_BROADWELL(dev_priv))
> dev_priv->display.init_clock_gating =
> broadwell_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0599408..697574f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> u32 mask;
>
> mask = DC_STATE_EN_UPTO_DC5;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> mask |= DC_STATE_EN_DC9;
> else
> mask |= DC_STATE_EN_UPTO_DC6;
> @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> gen9_assert_dbuf_enabled(dev_priv);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
> }
>
> @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> max_dc = 2;
> mask = 0;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> max_dc = 1;
> /*
> * DC9 has a separate HW flow from the rest of the DC states,
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