v2: Removing checks for vma obj and kmap_atomic validity. (Chris)
v3: Rebase.
v4: Updated to make sure SLPC enable keeps min/max freq softlimits
unchanged after initializing once. (Chris)
v5: s/first_enable/i915_load_enable. Updating freq softlimits after
checking that SLPC has indicated status as RUNNING in the shared
data. i915_load_enable is used to read default parameters set by
SLPC like min and max frequency on boot. Post that on re-activation
of SLPC, user set min and max frequencies will be communicated to SLPC.
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 27 +++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 941e573..be5f24f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -418,6 +418,26 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
0);
+ if (dev_priv->guc.slpc.i915_load_enable) {
+ /* Ask SLPC to operate within min/max freq softlimits */
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq));
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq));
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq));
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq));
+ }
+
kunmap_atomic(data);
host2guc_slpc_reset(dev_priv);
@@ -493,6 +513,13 @@ bool intel_slpc_get_status(struct drm_i915_private
*dev_priv)
switch (data.global_state) {
case SLPC_GLOBAL_STATE_RUNNING:
/* Capture required state from SLPC here */
+ dev_priv->guc.slpc.i915_load_enable = true;
+ dev_priv->guc.slpc.max_unslice_freq =
+ data.task_state_data.max_unslice_freq *
+ GEN9_FREQ_SCALER;
+ dev_priv->guc.slpc.min_unslice_freq =
+ data.task_state_data.min_unslice_freq *
+ GEN9_FREQ_SCALER;
ret = true;
break;
case SLPC_GLOBAL_STATE_ERROR:
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index c373f39..47653eb 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -121,6 +121,7 @@ struct slpc_shared_data {
struct intel_slpc {
bool active;
struct i915_vma *vma;
+ bool i915_load_enable;
/* i915 cached SLPC frequency limits */
u32 min_unslice_freq;
--
1.9.1
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