On Tue, May 08, 2012 at 01:49:36PM +0200, Daniel Vetter wrote: > On Fri, May 04, 2012 at 05:18:14PM -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni <[email protected]> > > > > Gen3+ is 13 bits (12:0), and on gen2 only 12 (11:0). For both the high > > bits are marked reserved, read-only so continue to mask them. Bit 31 > > is not reserved and has a meaning. > > > > Signed-off-by: Paulo Zanoni <[email protected]> > > Reviewed-by: Chris Wilson <[email protected]> > Queued for -next, thanks for the patch. While reading through the code > I've noticed that there are other places where we get this wrong. In the > crt load detect code we don't even bother with properly masking, and in > the precise vblank timestamp code we always use the gen3+ mask. That code > in addition doesn't properly handle the lack of the PIPEDSL register on > ilk+. Can I volunteer you to look into that?
Scrap the last remark, if mixed up PIPEDSL with PIPESTAT. -Daniel -- Daniel Vetter Mail: [email protected] Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
