From: Dhanya <[email protected]> For GLK, we need to program new register PLANE_COLOR_CTL for enabling CSC and Gamma. This patch sets the pipe gamma and pipe csc bit in the PLANE_COLOR_CTL.
Signed-off-by: Dhanya <[email protected]> --- drivers/gpu/drm/i915/intel_color.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index f0f2d04..8bfcdcd 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -538,7 +538,7 @@ void intel_color_init(struct drm_crtc *crtc) dev_priv->display.load_luts = haswell_load_luts; } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) { + IS_COFFEELAKE(dev_priv) || IS_GEN9_LP(dev_priv)) { dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; dev_priv->display.load_luts = broadwell_load_luts; } else { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 266b03f..d91a456 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3441,9 +3441,19 @@ static void skylake_update_primary_plane(struct drm_plane *plane, int dst_w = drm_rect_width(&plane_state->base.dst); int dst_h = drm_rect_height(&plane_state->base.dst); - plane_ctl = PLANE_CTL_ENABLE | - PLANE_CTL_PIPE_GAMMA_ENABLE | - PLANE_CTL_PIPE_CSC_ENABLE; + plane_ctl = PLANE_CTL_ENABLE; + + if (IS_GEN9_LP(dev_priv) && !IS_BROXTON(dev_priv)) { + I915_WRITE(PLANE_COLOR_CTL(pipe, 0), + PLANE_CTL_PLANE_GAMMA_DISABLE | + PLANE_CTL_PIPE_GAMMA_ENABLE | + PLANE_CTL_PIPE_CSC_ENABLE); + } else { + plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE | + PLANE_CTL_PIPE_CSC_ENABLE | + PLANE_CTL_PLANE_GAMMA_DISABLE; + } + plane_ctl |= skl_plane_ctl_format(fb->format->format); plane_ctl |= skl_plane_ctl_tiling(fb->modifier); @@ -3466,8 +3476,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane, I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); - if (IS_GEMINILAKE(dev_priv)) - I915_WRITE(PLANE_COLOR_CTL(pipe, 0), PLANE_GAMMA_DISABLE); if (scaler_id >= 0) { uint32_t ps_ctrl = 0; -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
